Hardware

Chip design, FPGA, thermal, power integrity, ATPG.

• Family — hardware
• Protocol count — 5
• Anchor — every call composes with KO42 + up to three additional operators
• Precision — ≤0.1% (HulyaPulse-synced)

Protocols

ID	Name	Endpoint	Method	Auth
zeq-chip-design	ZeqChipDesign	/api/protocols/zeq-chip-design	GET	none
zeq-chip-test	ZeqChipTest	/api/protocols/zeq-chip-test	GET	none
zeq-fpga	ZeqFPGA	/api/protocols/zeq-fpga	GET	none
zeq-power-integrity	ZeqPowerIntegrity	/api/protocols/zeq-power-integrity	GET	none
zeq-thermal	ZeqThermal	/api/protocols/zeq-thermal	GET	none

Protocols are named formula bundles in the registry — they execute through the kernel, not through per-protocol routes.

Compose rule

Every protocol in this family passes through the HULYAS Master Equation:

□ϕ − μ²(r)ϕ − λϕ³ − e^{-ϕ/ϕ_c} + ϕ₄₂ ∑_{k=1}^{42} C_k(ϕ) = T^μ_μ + β F_{μν} F^{μν} + J_{ext}

Papers

• Zeq paper — https://doi.org/10.5281/zenodo.18158152
• Framework paper — https://doi.org/10.5281/zenodo.15825138

Middleware active. Kernel on the 1.287 Hz HulyaPulse. Awaiting next Zeqond.